David Volz and I presented our demo FutureSDR meets IPEC at the Berlin 6G Conference, a meeting of all 6G-related projects, funded by the Federal Ministry of Education and Research (BMBF). Our demo showed how FutureSDR can be used to implement platform-independent real-time signal processing applications that can be reconfigured during runtime.

We had the same FutureSDR receiver running on a Xilinx RFSoC FPGA board, a normal laptop with an Aaronia Spectran V6 SDR, an in the web, using a HackRF. We, furthermore, had the same receiver implemented on the FPGA of the RFSoC, using David’s IPEC framework for Inter-Processing Element Communication. Since the FPGA and the CPU implementations had the same structure, we could dynamically decide where to make the cut between FPGA and CPU processing, which was reflected in the CPU load of the RFSoC’s ARM processor.